This question was previously asked in

LPSC (ISRO) Technical Assistant (Electronics): Official Paper 2016 (Held On 07 Aug 2016)

Option 2 : Higher than that of flash type ADCs

CT 1: Current Affairs (Government Policies and Schemes)

54560

10 Questions
10 Marks
10 Mins

**Explanation:**

In dual slope type ADC, the integrator generates two different ramps, one with the known analog input voltage VA and another with a known reference voltage –Vref. Hence it is called a dual-slope A to D converter. The logic diagram for the same is shown below.

The dual ramp output waveform is shown below:

The Output Voltage of Integrator is given by:

- \({V_0} = - \frac{{{V_a}RC}}{{{T_1}}} + \frac{{{V_{ref}}\left( {t - {T_1}} \right)}}{{RC}}\)
- It is mostly used in digital voltmeters.
- In the dual-slope A/D converter, the leakage current of the capacitor can cause errors in the integration and consequentially, an error.
- These effects, in the dual-slope AID converter, will manifest themselves as a reading of the DVM when no input voltage is present.

**Its main disadvantage is of slow conversion rate and also due to the integration process during input hold time.**

Hence flash type ADC needs only one clock with minimum conversion time.

So input hold time of dual slope type ADC is higher than that of flash type ADCs.

Hence **option** **(2) **is the correct answer.

__Important Points__

The conversion time of different types of ADC is shown :

Type of ADC |
No. of Clocks |
Time |

Counter Type |
2n-1 |
2n-1 Tclk |

SAR |
n |
nTclk |

Flash |
1 |
Tclk |

Dual Slope |
2n+1 |
2n+1 Tclk |

- From the above table, it is clear that the dual-slope is the slowest ADC, and Flash Type is the fastest ADC.
- The conversion type of Flash type is independent of the number of bits.
- As we require (2n – 1) comparators for n-bit conversion, the circuit is complex and expensive.
- These are employed on very high-speed digital acquisition systems.